Sudhind Dhamankar

Sudhind has lead development of digital designs in the domain of GSM/WCDMA transceivers, TV tuners, Error Correction IPs for FPGAs, ADSL Codecs, Video DACs and TMDS receivers. He has delivered 130nm-40nm designs taking up roles in architecture development, clocking, RTL design, Verification, Synthesis and backend. He has also worked extensively on optimizing signal processing designs for area and power.

He has led development of highly automated robust mixed signal verification methodology for DRP complex RF SoCs significantly shortening verification cycle time and improving quality of verification .

Sudhind has 10+ years of industry experience at companies like Lattice Semiconductor and TI, holds 4 US patents with 2 pending approval in areas of digital architecture and mixed signal verification. He is an alumnus of IIT Bombay.