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IO IPs

Sankalp offers high quality, silicon proven and ESD tested IOs so that the customer can achieve faster time to market and lower cost.

With each IO cell our deliverables are:
  • Technical Specifications
  • GDSII Layout
  • LVS netlist
  • LEF file
  • System level integration
  • Verilog Model
  • Timing Model
  • Application notes
  • Support

Status of IO IPs we own is shown in the table below:

Interface / IO Type Technology GDSII Si Proven ESD Tested Eval Board
LVDSRX IO 65nm GP TSMC √ √ √ X
IO 40nm GP TSMC √ √ √ X
IO 45nm LP TSMC 2Q’11 3Q’11 3Q’11 X
LVDSTX IO 65nm GP TSMC √ √ √ X
IO 40nm GP TSMC √ 1Q’11 1Q’11 X
IO 40nm LP TSMC 2Q’11 3Q’11 3Q’11 X
LVTTL33/25 combo IO 65nm GP TSMC √ √ √ X
LVCMOS18 IO 40nm GP TSMC √ √ √ X
IO 40nm LP TSMC 2Q’11 3Q’11 3Q’11
LVCMOS25 IO 40nm GP TSMC √ 1Q’11 1Q’11 X
LVCMOS33/25 Combo IO 40nm GP TSMC √ 1Q’11 1Q’11 X
DDR2 IO 65nm GP TSMC √ √ √ X
DDR3 IO 65nm LP UMC 1Q’11 3Q’11 3Q’11 X

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