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Sankalp Semiconductor having built expertise in the Analog and Mixed signal domain started its Interface Services & Solutions group to focus on IO cells and PHYs. This division has customized its design flow and methodologies to support efficient and high quality development of IO cells. IO cells are needed for all digital interface designs such as LVDS, HDMI, LVCMOS, Ethernet, DDR, USB, I2C, PCI Express and SerDes.
Some of the blocks we have worked on are listed below:
MIPI D-PHY
A MIPI D-PHY has been designed, with three lane interface designed into High Speed and Low Power modes, Self sustained with build-in LDO, PLL & Bandgap. The module achieved First Pass Parametric Success in all modes. It has been characterized in IOL UNH lab
SerDes Reference Clock Buffer
This buffer converts differential HSCL to differential CMOS / single ended CMOS.
It was designed for supply Independent biasing with duty cycle correction and jitter reduction.
Power on Reset
These circuits detect the power applied to the chip and generate a reset impulse that goes to the entire circuit placing it into a known state.
General Purpose IO’s ( IP’s Available)
Consist of LVTTL, LVDS,LVCMOS, DDR2, Analog pads, Thermal diode & Power Pads which are designed to reduce mask cost by low voltage oxide devices overdriven to higher voltages. These cells are Flip chip & wire bond compatible, Silicon Proven, ESD & SI Tested.
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