A wide array of over two hundred projects have been executed in physical design at Sankalp covering almost all the domains in the Analog and Mixed Signal field in different process nodes and many fabs. With proven expertise in Analog/Mixed Signal Layout from offsite for multiple customers at an optimal cost, Sankalp Semiconductor has been the vendor of choice for various customers looking at this niche and captive market of physical design in Analog and Mixed Signal.

Data Converters
Physical Design for stand-alone Data Converters for High Precision Analog, Ethernet and Radio Frequency applications has been executed with silicon success. Apart from this custom Data Converters in flash, pipeline and successive approximation architecture based modules and Resistor Interpolating DACs have been delivered.

Precision Analog and Baseband Circuits
Precision Layout demanding craft and diligence on behalf of the physical design engineer have been taken up. Physical Design for Analog Multiplexers and Temperature Sensors has been undertaken. Other circuits, operating at audio and baseband frequencies, have been driven by the advent of the SoCs. Baseband Full chip physical design for Audio and Baseband frequency circuits has been executed with Class AB and Class D architectures.

Radio Frequency Circuits
Sankalp’s RF Layout Design has expertise in modules going into Consumer Electronics and Wireless Systems. Within a short span of time, Sankalp has acquired considerable RF Layout physical design expertise in many typical blocks of RF circuits. Few of the blocks executed in this domain are Low Noise Amplifier (LNA), Mixers, IF Amplifiers, Voltage Controlled Oscillators (VCO), Pipeline ADCs of RF SoCs.

Power Management Circuits
A wide range of physical designs in this domain have been delivered ranging from silicon proven DC to DC Buck Convereters to Low Dropout Regulators with a wide array of architectures. Bandgap Reference Circuits, Reference Generators modules amongst other Power Management Modules have been done at Sankalp Semiconductor.

Test Chip and Process Validation
Various projects for the Figure of Merit Analysis of an evolving node, YRC and Yield related checks of Test Chips have been undertaken at Sankalp. These also include Raphael (Synopsys) based simulations of the evolving nodes.

ESD cells
Physical design of Transmission Line Test Structures which are a part of ESD protection circuitry on silicon have been executed at Sankalp.
The CAD platforms that have been used are Cadence Virtuoso, Magma Titan and Silicon Canvas’s Laker. Numerous automations on Cadence’s skill, Magma and Silicon Canvas’s tcl platform have been incorporated to reduce cycle time of the physical designs.