Key Offerings
- Synthesis
- Static Timing Analysis
- DFT
- Test time reduction
- Scan compression (XOR, MISR), Logic BIST
- At speed Memory BIST & repair
- Constraints and Timing
- Floor planning
- Power Grid/ IO and block placement
- Clock Tree Synthesis
- ATPG
- Stuckkat, LOC/LOS, path delay
- Fault grading
- Physical Verification (LVS, DRC, ERC)
- Multi-corner Multi-mode analysis
- Run Sign-off verification